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19-2134; Rev 1; 7/03
SPI-Compatible RTC in a TDFN
General Description
The MAX6902 SPITM-compatible real-time clock contains a real-time clock/calendar and 31 x 8 bits of static random-access memory (SRAM). The real-time clock/calendar provides seconds, minutes, hours, day, date, month, year, and century information. A time/date programmable polled ALARM is included in the MAX6902. The end-of-the-month date is automatically adjusted for months with fewer than 31 days, including corrections for leap year up to the year 2100. The clock operates in either the 24hr or 12hr format with an AM/PM indicator. The MAX6902 operates with a supply voltage of +2V to +5.5V, is available in the ultra-small 8-pin TDFN package, and works over the -40C to +85C industrial temperature range.
Features
o Real-Time Clock Counts Seconds, Minutes, Hours, Day of Week, Date of Month, Month, Year, and Century o Leap-Year Compensation Valid up to Year 2100 o +2V to +5.5V Wide Operating Voltage Range o SPI Interface: 4MHz at 5V; 1MHz at 2V o 31 x 8-Bit SRAM for Scratchpad Data Storage o Uses Standard 32.768kHz, 12.5pF Watch Crystal o Low Timekeeping Current (400nA at 2V) o Single-Byte or Multiple-Byte (Burst Mode) Data Transfer for Read or Write of Clock Registers or SRAM o Ultra-Small 8-Pin 3mm x 3mm x 0.8mm TDFN Package o Programmable Time/Date Polled ALARM Function o No External Crystal Bias Resistors or Capacitors Required
MAX6902
Applications
Point-of-Sale Equipment Intelligent Instruments Fax Machines Battery-Powered Products Portable Instruments
Ordering Information
PART MAX6902ETA-T TEMP RANGE -40C to +85C PINPACKAGE 8 TDFN TOP MARK AGT
Related Real-Time Clock Products
PART MAX6900 MAX6901 MAX6902 SERIAL INTERFACE I2CTM compatible 3 Wire SPI compatible SRAM 31 8 31 8 31 8 ALARM FUNCTION -- Polled Polled OUTPUT FREQUENCY -- 32kHz -- PINPACKAGE 6 TDFN 8 TDFN 8 TDFN
Typical Operating Circuit
+3.3V 0.1F 6 +3.3V VCC MAX6902 1 c 5 2 3 SCLK CS DOUT DIN GND 4 X1 8 32.768kHz CRYSTAL
Pin Configuration
TOP VIEW
SCLK 1 DOUT DIN 2
8 7
X1 X2 VCC CS
X2
7
MAX6902
3 6 5 GND 4
TDFN
I2C is a trademark of Philips Corp. Purchase of I2C components of Maxim Integrated Products, Inc., or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. SPI is a trademark of Motorola, Inc. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
SPI-Compatible RTC in a TDFN MAX6902
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V to +6V All Other Pins to GND ................................-0.3V to (VCC + 0.3V) Current into Any Pin..........................................................20mA Rate of Rise, VCC ............................................................100V/s Continuous Power Dissipation (TA = +70C) 8-Pin TDFN (derate 24.4mW/C above +70C) ..........1951.0mW Junction Temperature .....................................................+150C Storage Temperature Range........................ -65C to +150C ESD Protection (all pins, Human Body Model) ..................2000V Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.0V to +5.5V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Note 1)
PARAMETER Operating Voltage Range Active Supply Current (Note 2) Timekeeping Supply Current (Note 3) SYMBOL VCC ICC ITK VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VCC = +2V VCC = +5V VIN = 0 to VCC -10 10 15 VOL VOH VCC = +2.0V, ISINK = 1.5mA VCC = +5.0V, ISINK = 4mA VCC = +2.0V, ISOURCE = -0.4mA VCC = +5.0V, ISOURCE = -1mA 1.8 4.5 0.4 0.4 1.4 2.2 0.6 0.8 10 0.4 1.3 CONDITIONS MIN 2 TYP MAX 5.5 0.3 1.1 0.8 2.2 UNITS V mA A
SPI DIGITAL INPUTS (SCLK, DIN, CS) Input High Voltage Input Low Voltage Input Leakage VIH VIL IIL V V nA pF pF V V
Input Capacitance SPI DIGITAL OUTPUTS (DOUT) Output Capacitance Output Low Voltage Output High Voltage
2
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SPI-Compatible RTC in a TDFN
AC ELECTRICAL CHARACTERISTICS
(VCC = +2.0V to +5.5V, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.) (Figure 5, Notes 1, 4)
PARAMETER OSCILLATOR X1 to Ground Capacitance X2 to Ground Capacitance SPI SERIAL TIMING Maximum Input Rise Time Maximum Input Fall Time Output Rise Time Output Fall Time SCLK Period SCLK High Time SCLK Low Time SCLK Fall to DOUT Valid DIN to SCLK Setup Time DIN to SCLK Hold Time SCLK Rise to CS Rise Hold Time CS High Pulse Width CS High to DOUT High Impedance CS to SCLK Setup Time trIN tfIN trOUT tfOUT tCP tCH tCL tDO tDS tDH tCSH tCSW tCSZ tCSS 100 CLOAD = 100pF 100 2 2 200 100 DIN, SCLK, CS DIN, SCLK, CS DOUT, CLOAD = 100pF DOUT, CLOAD = 100pF VCC = +2V VCC = +5V 1000 238 100 100 100 2 2 10 10 s s ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX6902
25 25
pF pF
Note 1: All parameters are 100% tested at TA = +25C. Limits over temperature are guaranteed by design and characterization and not production tested. Note 2: ICC is specified with DOUT open, CS = DIN = GND, SCLK = 4MHz at VCC = +5V; SCLK = 1MHz at VCC = +2.0V. Note 3: Timekeeping current is specified with CS = VCC, SCLK = DIN = GND, DOUT = 100k to GND. Note 4: All values referred to VIH min and VIL max levels.
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SPI-Compatible RTC in a TDFN MAX6902
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
TIMEKEEPING CURRENT vs. SUPPLY VOLTAGE
MAX6902 toc01
10.0
SUPPLY CURRENT (A)
1.0
0.1 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 SUPPLY VOLTAGE (V)
Pin Description
PIN 1 2 3 4 5 6 7 8 NAME SCLK DOUT DIN GND CS VCC X2 X1 FUNCTION Serial Clock Input. SPI clock for DIN and DOUT data transfers. SPI Data Output SPI Data Input Ground Chip Select Input. Active low for valid data transfers. Power-Supply Pin. Bypass VCC to GND with a 0.1F capacitor. External 32.768kHz Crystal External 32.768kHz Crystal
Table 1. Acceptable Quartz Crystal Parameters
PARAMETER Frequency Equivalent Series Resistance (ESR) Parallel Load Capacitance Q Factor SYMBOL f MIN TYP 32.768 MAX UNITS kHz
RS
40
60
k
CL Q
11.2 40,000
12.5
13.7 60,000
pF
Detailed Description
The MAX6902 is a real-time clock/calendar with an SPIcompatible interface and 31 x 8 bits of SRAM. It provides seconds, minutes, hours, day of the week, date of the month, month, and year information, held in seven 8bit timekeeping registers (Functional Diagram). An onchip 32.768kHz oscillator circuit requires only a single external crystal to operate. Table 1 specifies the parameters for the external crystal, and Figure 1 shows a functional schematic of the oscillator circuit. The MAX6902's register addresses and definitions are described in Figure 2 and in Table 2. Time and calendar data are stored in the registers in binary-coded decimal (BCD) format. A polled alarm function is included for scheduled timing of user-defined times or intervals.
4
MAX6902
25pF
25pF
X1 EXTERNAL CRYSTAL
X2
Figure 1. Crystal Oscillator Circuit Schematic
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SPI-Compatible RTC in a TDFN MAX6902
REGISTER ADDRESS FUNCTION CLOCK SECONDS RD 0 /W MINUTES RD 0 /W HOURS RD 0 /W 0 0 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 1 00-59 *POR STATE 00-59 *POR STATE 00-23 01-12 *POR STATE 01-28/29 01-30 0-31 *POR STATE 0 0 1 0 0 1 01-12 *POR STATE 0 0 1 0 1 1 01-07 *POR STATE 0 0 1 1 0 1 00-99 *POR STATE 0 0 1 1 1 1 *POR STATE 0 1 0 0 1 1 00-99 *POR STATE 0 0 WP 0 0 0 ALM OUT 0 12/24 0 1/0 0 0 0 0 10 SEC 0 0 0 1 SEC 0 0 0 A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 D3 D2 D1 D0
10 MIN 0 0 0
1 MIN 0 0 0
10 HR 10 A/P HR 0/1 0 0 0
1 HR
0
0
0
DATE
RD 0 /W
0
0
0
1
1
1
0 0 0 0 0 0
0 10 DATE 0 0 0 0 0 0 0 0
1 DATE 0 0 1
MONTH
RD 0 /W
0 10M 0 0 0 0 0 0 0 0 0
1 MONTH 0 0 1
DAY
RD 0 /W
WEEK DAY 0 0 1
YEAR
RD 0 /W
10 YEAR 1 0 0 1 0 0 1 0 0 0 0 0
1 YEAR 0 0 0 0 0 0 0 0 0
CONTROL
RD 0 /W
CENTURY
RD 0 /W
1000 YEAR 0 0 1 1
100 YEAR 0 0 1
Note: *POR STATE defines power-on reset state of register contents.
Figure 2. Register Address Definition (Sheet 1 of 3)
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SPI-Compatible RTC in a TDFN MAX6902
REGISTER ADDRESS FUNCTION A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 MONTH D3 D2 D1 MINUTE 0 1 1 1 1 1 1 1 1 1 D0 SECOND 0 1 1 1 1 1 1 1 1 1
ALARM CONFIG
RD 0
0
1
0
1
0
1
0
/W RESERVED Do not write to this location. ALARM THRESHOLDS SECONDS RD 0 /W MINUTES RD 0 /W HOURS RD 0 /W 0 1 1 1 0 1 0 1 1 0 1 1 0 1 1 0 0 1 RD 0 /W 0 1 0 1 1 1
*POR STATE
0 0
0 0 0
0 0 0
0 0 0
0 0 0
*POR STATE
0
00-59 *POR STATE 00-59 *POR STATE 00-23 01-12 *POR STATE 01-28/29 01-30 01-31 *POR STATE
0 0 0 0 12/24 0 1/0 1 0 1 1
10 SEC 1 10 MIN 1 1 1 1 1
10 10 HR HR A/P 0/1 1 1 1
DATE
RD 0 /W
0
1
1
1
1
1
0 0 0 0 0 0
0 0 0 0 0 0
10 DATE 1 1 1
MONTH
RD 0 /W
1
0
0
0
0
1
01-12 *POR STATE
0 10M 0 0 0 1 0 0 1 0 0
1 MONTH 1
DAY
RD 0 /W
1
0
0
0
1
1
01-07 *POR STATE
YEAR
RD 0 /W
1
0
0
1
0
1
00-99 *POR STATE 1
10 YEAR 1 1 1 1
1 YEAR 1
CLOCK BURST
RD 0 /W
1
1
1
1
1
1
Figure 2. Register Address Definition (Sheet 2 of 3)
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HOUR 0 1 1 1 1 1 1 1
YEAR
DATE
DAY
1 SEC
1 MIN
1 HR
1 DATE
WEEK DAY
SPI-Compatible RTC in a TDFN MAX6902
REGISTER ADDRESS FUNCTION RAM RAM 0 * * * RAM 30 RD 1 /W RAM BURST RD 1 /W Note: *POR STATE defines power-on reset state of register contents. 1 1 1 1 1 1 1 RD 1 /W * * * 1 1 1 0 1 * * * RAM DATA 30 x x x * * * x x x x x 0 0 0 0 0 1 RAM DATA 0 x x x x x x x x A7 A6 A5 A4 A3 A2 A1 A0 VALUE D7 REGISTER DEFINITION D6 D5 D4 D3 D2 D1 D0
Figure 2. Register Address Definition (Sheet 3 of 3)
Table 2. Register Address and Description
WRITE (HEX) 01 03 05 07 09 0B 0D 0F 13 15 17 19 1B 1D 1F 21 23 25 3F READ (HEX) 81 83 85 87 89 8B 8D 8F 93 95 97 99 9B 9D 9F A1 A3 A5 BF DESCRIPTION Seconds Minutes Hours Date Month Day Year Control Century Alarm Configuration Reserved Seconds Alarm Threshold Minutes Alarm Threshold Hours Alarm Threshold Date Alarm Threshold Month Alarm Threshold Day Alarm Threshold Year Alarm Threshold Clock Burst POR CONTENTS (HEX) 00 00 00 01 01 01 70 00 19 00 07 7F 7F BF 3F 1F 07 FF Not applicable
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SPI-Compatible RTC in a TDFN MAX6902
Table 2. Register Address and Description (continued)
WRITE (HEX) 41 43 45 47 49 4B 4D 4F 51 53 55 57 59 5B 5D 5F 61 63 65 67 69 6B 6D 6F 71 73 75 77 79 7B 7D 7F READ (HEX) C1 C3 C5 C7 C9 CB CD CF D1 D3 D5 D7 D9 DB DD DF E1 E3 E5 E7 E9 EB ED EF F1 F3 F5 F7 F9 FB FD FF DESCRIPTION RAM 0 RAM 1 RAM 2 RAM 3 RAM 4 RAM 5 RAM 6 RAM 7 RAM 8 RAM 9 RAM 10 RAM 11 RAM 12 RAM 13 RAM 14 RAM 15 RAM 16 RAM 17 RAM 18 RAM 19 RAM 20 RAM 21 RAM 22 RAM 23 RAM 24 RAM 25 RAM 26 RAM 27 RAM 28 RAM 29 RAM 30 RAM Burst POR CONTENTS (HEX) Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Not applicable
8
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SPI-Compatible RTC in a TDFN
Command and Control
Address/Command Byte
Each data transfer into or out of the MAX6902 is initiated by an Address/Command byte. The Address/Command byte specifies which registers are to be accessed, and if the access is a read or a write. Figure 2 shows the Address/Command bytes and their associated registers, and Table 2 lists the hex codes for all read and write operations. The Address/Command bytes are input MSB (bit 7) first. Bit 7 specifies a write (logic 0) or read (logic 1). Bit 6 specifies register data (logic 0) or RAM data (logic 1). Bits 5-1 specify the designated register to be written or read. The LSB (bit 0) must be logic 1. If the LSB is a zero, writes to the MAX6902 are disabled. with a Seconds register increment. The updated time data are loaded into the timekeeping registers after the rising edge of CS, at the end of the SPI write operation. An incomplete write operation aborts the update procedure, and the contents of the input buffer are discarded. The timekeeping registers reflect the new time beginning with the first Seconds register increment after the rising edge of CS. Although both Single Writes and Burst Writes are possible, the best way to write to the timekeeping registers is with a Burst Write. With a Burst Write, the main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) and the Control register are written sequentially following the Address/Command byte. They must be written as a group of eight registers, with 8 bits each, for proper execution of the Burst Write function. All seven timekeeping registers are simultaneously loaded into the clock counters by the rising edge of CS, at the end of the SPI write operation. For a normal burst data transfer, the worst-case error that can occur between the actual time and the written time update is 1s. If single write operations are used to enter data into the timekeeping registers, error checking is required. If not writing to the Seconds register, begin by reading the Seconds register and save it as initial-seconds. Then write to the required timekeeping registers, and finally read the Seconds register again (final-seconds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. If writing to the Seconds register, update the Seconds register first, and then read it back and store its value (initial-seconds). Update the remaining timekeeping registers and then read the Seconds register again (final-seconds). Check to see that final-seconds is equal to initial-seconds. If not, repeat the write process. Note: After writing to any time or date register, no read or write operations are allowed for 45s.
MAX6902
Clock Burst Mode
Sending the Clock Burst Address/Command (3Fh for Write and BFh for Read), specifies burst-mode operation. In this mode, multiple bytes are read or written after a single Address/Command. The first seven clock/calendar registers (Seconds, Minutes, Hours, Date, Month, Day, and Year) and the Control register are consecutively read or written, starting with the MSB of the Seconds register. When writing to the clock registers in burst mode, all seven clock/calendar registers and the Control register must be written in order for the data to be transferred. See Example: Setting the Clock with a Burst Write.
RAM Burst Mode
Sending the RAM Burst Address/Command (F7h for Write, FFh for Read) specifies burst-mode operation. In this mode, the 31 RAM locations can be consecutively read or written, starting at 41h for Writes, and C1h for Reads. A Burst Read outputs all 31 bytes of RAM. When writing to RAM in burst mode, it is not necessary to write all 31 bytes for the data to transfer; each complete byte written is transferred to RAM. When reading from RAM, data are output until all 31 bytes have been read, or until CS is driven high.
AM/PM and 12Hr/24Hr Mode
Bit 7 of the Hours register selects 12hr or 24hr mode. When high, 12hr mode is selected. In 12hr mode, bit 5 is the AM/PM bit, logic high for PM. In 24hr mode, bit 5 is the second 10hr bit, logic high for hours 20 through 23.
Setting the Clock
Writing to the Timekeeping Registers
The time and date are set by writing to the timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year, and Century). During a write operation, an input buffer accepts the new time data while the timekeeping registers continue to increment normally, based on the crystal counter. The buffer also keeps the timekeeping registers from changing as the result of an incomplete write operation, and collision-detection circuitry ensures that a Time Write does not occur coincident
Write-Protect Bit
Bit 7 of the Control register is the Write-Protect bit. When high, the Write-Protect bit prevents write operations to all registers except itself. After initial settings are written to the timekeeping registers, set the WriteProtect bit to logic 1 to prevent erroneous data from entering the registers during power glitches or interrupted serial transfers. The lower 7 bits (bits 0-6) are
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SPI-Compatible RTC in a TDFN MAX6902
unusable, and always read zero. Any data written to bits 0-6 are ignored. Bit 7 must be set to zero before a single write to the clock, before a write to RAM, or during a Burst Write to the clock. The timekeeping registers may also be read using Single Reads. If Single Reads are used, it is necessary to do some error checking on the receiving end, because it is possible that the clock counters could change during the Read operations, and report inaccurate time data. The potential for error is when the Seconds register increments before all the registers are read. For example, suppose a carry of 13:59:59 to 14:00:00 occurs during single read operations. The net data read could be 14:59:59, which is erroneous. To prevent errors from occurring with single read operations, read the Seconds register first (initial-seconds) and store this value for future comparison. After the remaining timekeeping registers have been read, reread the Seconds register (final-seconds). Check that the final-seconds value equals the initial-seconds value. If not, repeat the entire Single Read process. Using Single Reads at a 100kHz serial speed, it takes under 2.5ms to read all seven of the timekeeping registers, including two reads of the Seconds register.
Example: Setting the Clock with a Burst Write
To set the clock to 10:11:31PM, Thursday July 4th, 2002 with a burst write operation, write 3Fh as the Address/Command byte, followed by 8 bytes, 31h, 11h, B0h, 04h, 07h, 05h, 02h, and 00h (Figure 2). 3Fh is the Clock Burst Write Address/Command. The first byte, 31h, sets the Seconds register to 31. The second byte, 11h, sets the Minutes register to 11. The third byte, B0h, sets the Hours register to 12hr mode, and 10PM. The fourth byte, 04h, sets the Date register (day of the month) to the 4th. The fifth byte, 07h, sets the Month register to July. The sixth byte, 05h, sets the Day register (day of the week) to Thursday. The seventh byte, 02h, sets the Year register to 02. The eighth byte, 00h, clears the Write-Protect bit of the Control register to allow writing to the MAX6902. The Century register is not accessed with a Burst Write and therefore must be written to separately to set the century to 20. Note the Century register corresponds to the thousand and hundred digits of the current year and defaults to 19.
Example: Reading the Clock with a Burst Read
To read the time with a Burst Read, send BFh as the Address/Command byte. Then clock out 8 bytes, Seconds, Minutes, Hours, Date of the month, Month, Day of the week, Year, and finally the Control byte. All data are output MSB first. Decode the required information based on the register definitions listed in Figure 2.
Reading the Clock
Reading the Timekeeping Registers
The main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year) can be read with either Single Reads or a Burst Read. In the MAX6902, a latch buffers each clock counter's data. Clock counter data are latched by the SPI Read Command (on the falling edge of SCLK, after the Address/Command byte has been sent by the master to read a timekeeping register). Collision-detection circuitry ensures that this does not happen coincident with a Seconds counter increment to ensure accurate time data are being read. The clock counters continue to count and keep accurate time during the read operation. The simplest way to read the timekeeping registers is to use a Burst Read. In a Burst Read, the main timekeeping registers (Seconds, Minutes, Hours, Date, Month, Day, Year), and the Control register are read sequentially, in the order listed with the Seconds register first. They are read out as a group of eight registers, with 8 bits each. All timekeeping registers (except Century) are latched upon the receipt of the Burst Read command. The worst-case error between the "actual" time and the "read" time is 1s for a normal data transfer.
Using the Alarm
A polled alarm function is available by reading the ALM OUT bit. The ALM OUT bit is D7 of the Minutes timekeeping register. A logic 1 in ALM OUT indicates the Alarm function is triggered. There are eight registers associated with the alarm function--seven programmable Alarm Threshold registers and one programmable Alarm Configuration register. The Alarm Configuration register determines which Alarm Threshold registers are compared to the timekeeping registers, and the ALM OUT bit sets if the compared registers are equal. Figure 2 shows the function of each bit of the Alarm Configuration register. Placing a logic 1 in any given bit of the Alarm Configuration register enables the respective alarm function. For example, if the Alarm Configuration register is set to 0000 0011, ALM OUT is set when both the minutes and seconds indicated in the Alarm Threshold registers match the respective timekeeping registers. Once set, ALM OUT stays high until it is cleared by reading or writing to the Alarm Configuration register, or by reading or writing to any of the Alarm Threshold registers. The Alarm Configuration register is written with address 15h, and read with address 95h.
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SPI-Compatible RTC in a TDFN
Using the On-Board RAM
The static RAM is 31 x 8 bits addressed consecutively in the RAM Address/Command space. Table 2 details the specific hex Address/Commands for Reads and Writes to each of the 31 locations of RAM. The contents of the RAM are static and remain valid for VCC down to 2V. All RAM data are lost if power is cycled. The WriteProtect Bit (bit 7 of the Control register), when high, disallows any writes to RAM. shifted out on the negative edge. There is one clock cycle for each bit transferred. Address and data bits are transferred in groups of eight. The SPI protocol allows for one of four combinations of serial clock phase and polarity from the microcontroller, through a 2-bit selection in its SPI Control register. The clock polarity is specified by the CPOL Control bit, which selects active-high or active-low clock, and has no significant effect on the transfer format. The Clock Phase Control bit, CPHA, selects one of two different transfer formats. The clock phase and polarity must be identical for the master and the slave. For the MAX6902, set the control bits to CPHA = 1 and CPOL = 1. This configures the system for data to be launched on the negative edge of SCLK and sampled on the positive edge. With CPHA equal to 1, CS can remain low between successive data byte transfers, allowing burst-mode data transfers to occur. Address and data bytes are shifted MSB first into DIN of the MAX6902, and out of DOUT. Data are shifted out at the negative edge of SCLK, and shifted in or sampled at the positive edge of SCLK. Any transfer requires an Address/Command byte followed by one or more bytes of data. Data are transferred out of DOUT for a read operation, and into DIN for a write operation. DOUT transmits data only after an Address/Command byte specifies a read operation; otherwise, it is high impedance. Data Transfer Write timing is shown in Figure 3. Data Transfer Read timing is shown in Figure 4. Detailed Read and Write Timing is shown in Figure 5.
MAX6902
SPI-Compatible Serial Interface
Interface the MAX6902 with a microcontroller using a serial, 4-wire, SPI interface. SPI is a synchronous bus for address and data transfer, and is used with Motorola or other microcontrollers that have an SPI port. Four connections are required for the interface: DOUT (Serial Data Out); DIN (Serial Data In); SCLK (Serial Clock); and CS (Chip Select). In an SPI application, the MAX6902 acts as a slave device and the microcontroller acts as the master. CS is asserted low by the microcontroller to initiate a transfer, and deasserted high to terminate a transfer. DIN transfers input data from the microcontroller to the MAX6902. DOUT transfers output data from the MAX6902 to the microcontroller. A shift clock, SCLK, is used to synchronize data movement between the microcontroller and the MAX6902. SCLK, which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. The inactive clock polarity is usually programmable on the microcontroller side of the SPI interface. In the MAX6902, input data are latched on the positive edge, and output data are
CS SCLK DIN
0
R*
A5
A4
A3
A2
A1
1
D7
D6
D5
D4 DATA BYTE
D3
D2
D1
D0
ADDRESS/COMMAND BYTE
DOUT * R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
Figure 3a. Single Write
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11
SPI-Compatible RTC in a TDFN MAX6902
CS SCLK
DIN
0
R*
1
1
1
1
1
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
ADDRESS/COMMAND BYTE**
DATA BYTE 1
DATA BYTE N
DOUT
HIGH IMPEDANCE; NO ACTIVITY ON DOUT LINE DURING WRITES.
* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. ** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
Figure 3b. Burst Write
CS SCLK DIN
1
R*
A5
A4
A3
A2
A1
1
ADDRESS/COMMAND BYTE DOUT HIGH IMPEDANCE
D7
D6
D5
D4
D3 DATA BYTE
D2
D1
D0
* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0.
Figure 4a. Single Read
CS SCLK DIN
1
R*
1
1
1
1
1
1
ADDRESS/COMMAND BYTE**
DOUT
HIGH IMPEDANCE
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
* R = RAM/REGISTER SELECT BIT; RAM = 1, REGISTER = 0. ** ONLY ONE ADDRESS/COMMAND BYTE IS REQUIRED PER BURST TRANSACTION.
DATA BYTE 1
DATA BYTE N
Figure 4b. Burst Read
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SPI-Compatible RTC in a TDFN MAX6902
tCSH CS tCSS SCLK tDH tDS
D7 D6 D5 D0
tCL
tCH
tCP
tCSW
DIN tCSZ D7 tDO D0
DOUT
Figure 5. SPI Bus Timing Diagrams
Chip Select
CS serves two functions. First, CS turns on the control logic that allows access to the Shift register for Address/Command and data transfer. Second, CS provides a method of terminating either single-byte or multiple-byte data transfers. All data transfers are initiated by driving CS low. If CS is high, then DOUT is high impedance.
Data Output (Single-Byte Read and Burst Read)
A read from the MAX6902 is initiated by an Address/Command Write from the microcontroller (master) to the MAX6902 (slave). The Address/Command Write portion of the data transfer is clocked into the MAX6902 on rising clock edges. Following the eighth falling clock edge of SCLK, after tDO (Figure 4) data begins to be output on DOUT of the MAX6902. Data bytes are output MSB first. Additional SCLK cycles transmit additional data bits, as long as CS remains low. This permits continuous burst-mode read capability.
Serial Clock
A clock cycle on SCLK is a rising edge followed by a falling edge. For data input, data must be valid at DIN before the rising edge of the clock. For data outputs, bits are valid on DOUT after the falling edge of the clock.
Applications Information
Crystal Selection
The MAX6902 is designed to use a standard 32.768kHz watch crystal. Table 1 details the recommended crystal requirements. Some suggested crystals are listed in Table 3. In addition to the specified SMT devices, some of the listed manufacturers also offer other package options.
Data Input (Single-Byte Write)
Following the eight SCLK cycles that input a Single-Byte Write Address/Command, data bits are input on the rising edges of the next eight SCLK cycles. Additional SCLK cycles are ignored. Input data MSB first.
Data Input (Burst Write)
Following the eight SCLK cycles that input a Burst-Write Address/Command, data bits are input on the rising edges of the following SCLK cycles. The number of clock cycles depends on whether the timekeeping registers or RAM are being written. A Clock Burst Write requires 1 Address/Command byte, 7 timekeeping data bytes, and 1 Control register byte. A Burst Write to RAM may be terminated after any complete data byte by driving CS high. Input data MSB first (Figure 3).
Frequency Stability and Temperature
Timekeeping accuracy of the MAX6902 is dependent on the frequency stability, of the external crystal. To determine frequency stability, use the parabolic curve in Figure 6 and the following equations: f = fk(T0 - T)2 where: f = change in frequency from +25C (Hz) f = nominal crystal frequency (Hz)
13
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SPI-Compatible RTC in a TDFN MAX6902
Table 3. 32.768kHz Surface-Mount Watch Crystals
MANUFACTURER MANUFACTURER PART NO. ABS25-32.768-12.5-B-2-T AWS2A-32.768KHz, AWS2B-32.768KHz ECS-.327-12.5-17 FSM327 SX2010/ SX2020 RSE-32.768-12.5-C-T 32S12A TEMP. RANGE -40C to +85C -20C to +70C -10C to +60C -40C to +85C -20C to +75C -10C to +60C -40C to +85C CL (pF) +25C FREQUENCY TOLERANCE (ppm) 20 20 20 20 20 20 20
Abracon Corporation Caliber Electronics ECS INC International Fox Electronics M-tron Raltron SaRonix
12.5 12.5 12.5 12.5 12.5 12.5 12.5
k = parabolic curvature constant (-0.035 0.005ppm/C2 for 32.768kHz watch crystals) T0 = turnover temperature (+25C 5C for 32.768kHz watch crystals) T = temperature of interest (C) For example: What is the worst-case change in oscillator frequency from +25C ambient to +45C ambient? fdrift = 32.768Hz x (-0.04ppm/ oC2 x (1x 10-6 )) x (20o C - 45o C)2 = -0.8192Hz What is the worst-case timekeeping error per second? Error due to temperature drift: t drift = 1/ (f + fdrift ) / 32,768 - 1s / 1s t drift
0
-40
-20
TEMPERATURE (C) 0 20 40 60
80
100
-50
f (ppm)
-100
-150
-200
-250
]] } {[ [ = {[1/[(32,768Hz - 0.8192Hz) / 32,768]] - 1s} / 1s
= 0.000025s / s
TYPICAL TEMPERATURE CHARACTERISTICS (k = -0.035 ppm/C2; TO = +25C)
Figure 6. Typical Temperature Curve for 32.768kHz Watch Crystal
After 1 month that translates to: hr min s t = (31day) 24 60 (0.000045s/s) 60 hr min day =120.528s Total worst-case timekeeping error at the end of 1 month at 45C is about 120s or 2min (assumes negligible parasitic layout capacitance).
Error due to 25C initial crystal tolerance of 20ppm: tinitial = 1/ (f + finitial ) / 32,768 - 1s / 1s
{[
[
finitial = 32,768Hz x -20ppm x (1 x 10-6 ) = 0.65536Hz Total timekeeping error per second: tinitial = 1/ (32,768 - 0.65536) / 32,768 - 1 / 1s = 0.000020s / s t total = t drift + tinitial t total = 0.000025s / s + 0.000020s / s = 0.000045s / s
(
]]
}
)
{[ [
]]
}
Oscillator Start Time
The MAX6902 oscillator typically takes 5s to 10s to begin oscillating. To ensure the oscillator is operating correctly, the software should validate proper timekeeping. This is accomplished by reading the Seconds register. Any reading of 1s or more from the POR value of zero seconds is a validation of proper startup.
14
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SPI-Compatible RTC in a TDFN
Timekeeping Current
When DOUT is high impedance (CS = high or during a DIN transfer segment), there is a potential for increased timekeeping current (up to 100x) if DOUT is allowed to float. If minimum timekeeping current is desired, then ensure DOUT is not allowed to float. The microcontroller port pin attached to DOUT could be configured as an input with a weak pullup. An alternate solution is to use a 100k, or less, pulldown or pullup resistor (for microcontroller port pins with 1A input leakage).
RESERVED Register
Address/Command 17h is reserved for factory testing ONLY. Do not write to this register. If inadvertent writes are done to this register, cycle power to the MAX6902.
MAX6902
Power-Supply Considerations
For most applications, a 0.1F capacitor from VCC to GND provides adequate bypassing for the MAX6902. A series resistor can be added to the supply line for operation in extremely harsh or noisy environments.
Timekeeping Current--Backup Battery Systems
Often a real-time clock (RTC) is operated in a system with a backup battery. A microprocessor supervisory circuit with backup battery switchover, or other switching arrangement, is used to switch power from VCC to VBATT when VCC falls below a set threshold. Most of these systems leave only the RTC and some SRAM to run from VBATT. The microcontroller that communicates with the RTC is powered only from V CC . When the microcontroller is put into reset, its ports typically become high impedance. This essentially floats DIN, CS, DOUT, and SCLK. There is a potential for increased timekeeping current (up to x100) as VCC falls through the linear region of the gates for DIN, CS, DOUT, and SCLK. Duration of this effect depends on the discharge rate of VCC. To minimize current draw from V BATT in such systems, ensure that V CC falls rapidly at power down. One option is a VCC discharge resistor of 100k or less from VCC to ground. This also ensures sufficient impedance, back through the microcontroller's ESD protection, on VCC when it is gone to keep DIN, CS, DOUT, and SCLK from floating, which can cause excessive timekeeping current. Alternately, a 100k pulldown (for microcontroller port pins with 1A input leakage) on each pin (DIN, CS, DOUT, and SCLK) ensures that timekeeping current specifications are met during the power switchover.
PC Board Layout Considerations
The MAX6902 uses a very-low-current oscillator to minimize supply current. This causes the oscillator pins, X1 and X2, to be relatively high impedance. Exercise care to prevent unwanted noise pickup. Connect the 32.768kHz crystal directly across X1 and X2 of the MAX6902. To eliminate unwanted noise pickup, design the PC board using these guidelines (Figure 7): 1) Place the crystal as close to X1 and X2 as possible and keep the trace lengths short. 2) Place a guard ring around the crystal, X1 and X2 traces (where applicable), and connect the guard ring to GND; keep all signal traces away from beneath the crystal, X1, and X2. 3) Finally, an additional local ground plane can be added under the crystal on an adjacent PC board layer. The plane should be isolated from the regular PC board ground plane, and tied to ground at the MAX6902 ground pin. 4) Restrict the plane to be no larger than the perimeter of the guard ring. Do not allow this ground plane to contribute significant capacitance between X1 and X2.
Chip Information
TRANSISTOR COUNT: 26,418 PROCESS: CMOS
Power-On Reset
The MAX6902 contains an integral POR circuit that ensures all registers are reset to a known state on power-up. Once VCC rises above 1.6V (typ), the POR circuit releases the registers for normal operation. When VCC drops to less than 1.6V (typ), the MAX6902 resets all register contents to the POR defaults (Figure 2).
______________________________________________________________________________________
15
SPI-Compatible RTC in a TDFN MAX6902
GROUND PLANE VIA CONNECTION
*
GUARD RING VCC PLANE VIA CONNECTION 0.1F SM CAP
* *
MAX6902
GROUND PLANE VIA CONNECTION
* ** **
* *
* * * ** ** LAYER 2 LOCAL GROUND4 PLANE CONNECT ONLY TO PIN
GROUND PLANE VIA
SM WATCH CRYSTAL
* ** *
GROUND PLANE VIA CONNECTION
*LAYER 1 TRACE
Figure 7. MAX6902 Crystal PC Board Layout
16
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SPI-Compatible RTC in a TDFN
Functional Diagram
X1 X2 OSCILLATOR 32.768kHz DIVIDER 1Hz SECONDS MINUTES HOURS DATE VCC GND SCLK DIN DOUT CS CONTROL LOGIC MONTH DAY INPUT SHIFT REGISTERS ADDRESS REGISTER YEAR CONTROL CENTURY ALARM CONFIG 31x 8 RAM RESERVED ALARM THRESHOLDS CLOCK BURST RAM BURST
MAX6902
ALARM OUT
ALARM CONTROL LOGIC
______________________________________________________________________________________
17
SPI-Compatible RTC in a TDFN MAX6902
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, QFN THIN.EPS
1 2
L D A A2
PIN 1 ID
D2
1
N
1
b
PIN 1 INDEX AREA
C0.35 [(N/2)-1] x e REF. e
E
DETAIL A
E2
A1
k
C L
C L
L e A e
L
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
APPROVAL DOCUMENT CONTROL NO. REV.
21-0137
D
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 0.20 MAX. 0.80 3.10 3.10 0.05 0.40
0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 N 6 8 10 D2 1.50-0.10 1.50-0.10 1.50-0.10 E2 2.30-0.10 2.30-0.10 2.30-0.10 e 0.95 BSC 0.65 BSC 0.50 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 b 0.40-0.05 0.30-0.05 0.25-0.05 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF
SEMICONDUCTOR
PROPRIETARY INFORMATION TITLE:
DALLAS
PACKAGE OUTLINE, 6, 8 & 10L, TDFN, EXPOSED PAD, 3x3x0.80 mm
APPROVAL DOCUMENT CONTROL NO. REV.
2 2
21-0137
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
18 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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